The present invention relates to a clock recovery circuit for recovering a reference clock signal from a digitally modulated signal and, more particularly, to a variable bit rate clock recovery circuit required for a data communication system with a variable bit rate.
Various circuits for recovering a reference clock signal from a digitally modulated signal have been proposed. FIG. 1 shows one of such conventional circuits. Referring to FIG. 1, a clock phase error detector 1, a loop filter 2, a D/A converter 3, and a voltage controlled oscillator (VCO) 4 constitute a clock recovery closed loop. The VCO 4 outputs a reference clock signal CLK. The clock phase error detector 1 receives a demodulated signal S.sub.DEM and the reference clock signal CLK, detects a phase difference between the two signals, and outputs the phase difference as a digitized time serial signal S.sub.ER. FIG. 2 shows an arrangement of the clock phase error detector 1. Referring to FIG. 2, the demodulated signal S.sub.DEM is supplied to an A/D converter 6. The reference clock signal CLK is supplied to a frequency multiplier 5, a phase error detector 7, and a zero-cross detector 8.
The frequency multiplier 5 supplies a sampling signal having a frequency twice that of the reference clock signal CLK to the A/D converter 6. The A/D converter 6 A/D-converts the demodulated signal S.sub.DEM by using the sampling signal. The digital output signal from the A/D converter 6 is input to the phase error detector 7 and the zero-cross detector 8. The phase error detector 7 selects an odd-numbered sampling signal, i.e., the sampled value at a zero-cross point of the demodulated signal S.sub.DEM. The zero-cross detector 8 selects an even-numbered sampling signal, i.e., the sampled value at a signal point of the demodulated signal S.sub.DEM, and outputs a signal representing the polarity of the selected signal to the phase error detector 7.
The phase error detector 7 multiplies the sampled value at the zero-cross point of the detected demodulated signal by the polarity of the sampled value at the signal point of the demodulated signal detected by the zero-cross detector 8, and obtains a phase error. The output from the phase error detector 7 represents a correct phase error only when the polarity is inverted at a signal point before or after the phase error detection point of the demodulated signal S.sub.DEM, i.e., at the zero-cross point. Therefore, when the zero-cross detector 8 detects that the polarity is inverted at a signal point before or after the phase error detection point of the demodulated signal S.sub.DEM, it outputs a zero-cross detection pulse to a selector 9. The selector 9 selects an output from the phase error detector 7 by using this zero-cross detection pulse. When the zero-cross pulse is not supplied, the selector 9 outputs a zero or outputs a value in the immediately preceding sampling period again. The outputs from the selector 9 become clock phase error signals S.sub.ER. When the timings of the demodulated signal S.sub.DEM and the reference clock signal CLK coincide with each other, the mean value of the clock phase error signals S.sub.ER converges to zero.
Referring to FIG. 1, an output from the clock phase error detector 1 is input to the loop filter 2. Then, high-frequency components are removed from the output in accordance with the low-pass filter characteristics of the loop filter 2. This loop filter 2 is generally constituted by an infinite impulse response digital filter and is an important factor determining a noise bandwidth and synchronization characteristics of the clock recovery closed loop. In addition, by simply replacing the loop filter 2 with multiplication of DC gain K, a primary type loop can be formed.
The digital time serial signal as the output from the loop filter 2 is converted into an analog signal by the D/A converter 3. The output frequency and phase of the voltage controlled oscillator 4 are controlled by the output voltage from the D/A converter 13, and the output from the voltage controlled oscillator 4 becomes the reference clock signal CLK.
In the above conventional reference clock recovery circuit, no specific problem is posed as long as a bit rate is fixed. However, various bit rates are employed in a small-capacity SCPC system such as a commercial communication, which is expected to be developed further in the future. Thus, it is desired that such system can flexibly respond to a changing/switching operation of these bit rates. From this viewpoint, the following problems are posed in the conventional reference clock recovery circuit.
(1) The VCO 4 (FIG. 2) must be replaced with another one every time a bit rate is changed. Therefore, a number of VCOs 4 corresponding to the number of types of bit rates must be prepared.
(2) It is impossible for all the VCOs 4 corresponding to the number of types of bit rates to have identical voltage control characteristics and frequency modulation characteristics. Therefore, a great modification of peripheral circuits is inevitably required in accordance with a VCO used every time a bit rate is changed.
(3) Cumbersome adjustment due to a change in bit rate is required for each replacement of the VCO 4.